1. Field of the Invention
This invention concerns latch circuitry and more particularly concerns latch circuitry that apertures an input signal, i.e., xe2x80x9cdata,xe2x80x9d and outputs a signal having a higher maximum voltage level, in effect shifting the maximum voltage level of the input signal.
2. Related Art
As systems-on-a-chip become more complex, the circuitry on a chip is increasingly put together from disparate designs. Moreover, to reduce power consumption on a chip it is common include some portions of logic circuitry that operate at a lower voltage (and thus lower power), and other portions, such as analog circuits or critical high speed circuits, that operate at a higher voltage due to design constraints. Consequently, it is increasingly necessary to patch together portions of logic circuitry using level shifting circuitry that operates across voltage domains. High-performance designs for such level shifting circuitry are more difficult for the case where an input signal has a lower maximum voltage than the desired output signal, that is, where the circuitry is in effect shifting from low to high voltage.
Besides needing to shift the voltage levels of circuitry portions, is also commonly necessary to synchronize the timing of circuitry portions at their interfaces using latch circuitry, which for testing purposes must often be scannable. Conventionally, the voltage level shifting and the latching functions are performed by distinctly different circuitry. Thus, at certain logic circuitry boundaries there conventionally exists both voltage level shifting circuitry and latching circuitry. This arrangement takes up more space and consumes more power on a chip that is desirable. Consequently, there is a need for improved voltage level shifting and latching circuitry.
The foregoing need is addressed in the present invention. According to one form of the invention latch circuitry has a first input stage for sampling a data input signal responsive to a first timing signal and generating a signal on an intermediate node in the latch circuitry. The latch circuitry also has a second input stage for sampling a scan input signal responsive to a second timing signal, and generating a signal on the intermediate node. The latch circuitry also has an output stage for generating an output signal on an output node of the latch circuitry responsive to the signal on the intermediate node and a third timing signal. The data input signal has a maximum voltage level and at least one stage of the latch circuitry is operable to effectively shift the voltage level so that the output signal has a higher maximum voltage level than that of the data signal. In this manner latch circuitry is integrated with level shifting circuitry, thereby reducing circuitry area and power consumption without adversely impacting functionality and performance.
Objects, advantages and other forms of the invention will become apparent upon reading the following detailed description and upon reference to the accompanying drawings.